The present invention relates to a marking apparatus for applying a "defective mark" to identify a defective chip, within a semiconductor wafer.
A semiconductor wafer has a plurality of semiconductor chips formed therein through the use of photolithographic and impurity diffusion processes. The wafer is tested with respect to the respective individual semiconductor chips by means of a test system which marks the defective chips. Thereafter, the wafer is cut into the separate chips.
The test system generally comprises one tester, a plurality of probers connected to this tester, and probe cards which are to be inserted into the respective probers. The includes a tester main body and a plurality of stations, each of which forms a part of the tester. One of the stations is provided for each prober. The prober includes a table for loading semiconductor wafer a marking apparatus and a prober controller.
At present, efforts are made to seek a speed-up of an operation speed of semiconductor integrated circuit devices, whose integration are more and more increased. In view of such current status of the art, a speed-up of testing and marking in a test system for semiconductor wafers has been also required.
In a test system in the prior art, however, the configuration of the marking apparatus used therein was a hindrance against a speed-up of an operation of the test system.